1. Field of the Invention
The present invention relates to a page buffer having a dual register, a semiconductor memory device having the same, and a program method thereof, and more particularly to, a page buffer having a dual register which can reduce a whole program time by reducing a program time in a normal program operation, a semiconductor memory device having the same, and a program method thereof.
2. Discussion of Related Art
Recently, there are increasing demands for a semiconductor memory device which has electrical program and erase functions and which does not need a refresh function of re-producing a data at intervals of a predetermined period. In addition, researches have been actively made on a high integration technology of a memory device to develop a large capacity memory device for storing a lot of data. Here, a program operation means an operation of writing a data on a memory cell, and an erase operation means an operation of erasing the data written on the memory cell.
A NAND type flash memory device in which a plurality of memory cells are connected in series to form one string (namely, adjacent cells share a drain or source) has been developed for high integration of the memory device. Differently from a NOR type flash memory device, the NAND type flash memory device sequentially reads information. The program and erase operations of the NAND type flash memory device are performed by controlling a threshold voltage of the memory cell, by implanting or emitting electrons to/from a floating gate according to an F-N tunneling method.
The NAND type flash memory device uses a page buffer for storing a large capacity of information in a short time. The page buffer receives a large capacity of data from an input/output pad, and transmits the data to the memory cells. The page buffer is generally comprised of a single register to temporarily store data, but recently comprised of a dual register to increase a program speed in the program operation of a large capacity of data in the NAND type flash memory device.
FIG. 1 is a circuit diagram illustrating a conventional page buffer having a dual register. In FIG. 1, P1 to P4 denote PMOS transistors, N1 to N18 denote NMOS transistors, and HN1 to HN4 denote high voltage NMOS transistors.
Referring to FIG. 1, the conventional page buffer having the dual register performs a program operation on a memory cell of a memory cell array 10 according to a data from an input/output pad. The conventional page buffer includes a cache register 40, and a main register 30 for receiving a data from the cache register 40, stores the data, and transmits the data to the memory cell array 10 according to the operation of a bit line selecting unit 20.
The operational characteristics of the conventional page buffer in the program operation will now be explained with reference to FIG. 1. In the program operation, an YA pad YA maintains a ground state. When data 1 is inputted from the input/output pad, a control signal DI1 which is a data-in signal is enabled to, turn on NMOS transistors N12 and N13. Accordingly, an input terminal QAb of a latch unit 42 of the cache register 40 is transited to a low level. Conversely, when data 0 is inputted from the input/output pad, a control signal nD1 which is a data-in signal is enabled to turn on an NMOS transistor N15. Therefore, an output terminal QA of the latch unit 42 of the cache register 40 is transited to a low level. That is, according to the data from the input/output pad, a data having a predetermined value is stored in the latch unit 42 of the cache register 40, transmitted to the main register 30 through an NMOS transistor N14 turned on by a control signal PDUMP via a node SN, and stored in a latch unit 32. The data stored in the latch unit 32 of the main register 30 is transmitted to the plurality of memory cells of the memory cell array 10 through the bit line selecting unit 20, thereby performing the program operation.
However, the conventional page buffer of FIG. 1 executes the above procedure both in the cache program operation and the normal program operation. Normally, the program operation is divided into the normal program operation, and the cache program operation for storing a data in the cache register 40 in advance and performing the program operation to increase the program speed. Here, the normal program operation means a program operation of programming data at a time, and the cache program operation means a program operation of consecutively programming data a few times. In general, in the normal program operation, a program operation command signal, an address signal, a data and a normal program command signal 10h for indicating the normal program operation are inputted to the input/output pad. On the other hand, in the cache program operation, a program operation command signal, an address signal, a data and a cache program command signal 15h for indicating the cache program operation are inputted. That is, the normal program operation and the cache program operation are distinguished by the normal program command signal and the cache program command signal.
As described above, in the conventional page buffer, the data is transmitted to the main register 30 through the cache register 40, and transmitted to the memory cell array 10 both in the normal program operation and the cache program operation. That is, the process for transmitting the data from the cache register 40 to the main register 30 is performed in the whole program operations (including the normal program operation and the cache program operation). It takes about 3 μs to transmit the data from the cache register 40 to the main register 30. The program speed increases in the cache program operation using the cache register 40 for programming a large capacity of data. However, a time for transmitting the data from the cache register 40 to the main register 30 is unnecessarily spent in the normal program operation.